The present invention relates to integrated-circuits and, in particular, to a circuit and method for testing power-on-reset circuitry in integrated circuits.
Many integrated circuits include power-on-reset circuitry to generate an automatic power-on-reset pulse. The power-on-reset pulse is used to initialize the integrated-circuit system during the "power-up" sequence that manages the transient conditions at the time the power supply Vcc is connected. When an integrated circuit has power-on-reset circuitry residing on-chip, one problem is the determination whether or not that power-on-reset circuitry functions properly. Preferably, the determination should be made without use of probes during manufacture and without dismantling the integrated-circuit chip after manufacture.
The output of the power-on-reset circuitry is a transient, one-shot pulse generated at the time the supply voltage Vcc is coupled to the circuit. This one-shot pulse is used, for example, to reset latches in the integrated circuit. Since the latches can default to the correct state without the need of the power-on-reset signal during the power-up sequence, the integrated circuit and/or system may function properly whether or not the power-on-reset circuitry is functioning properly.
In the prior-art, automatic test equipment has been used to directly observe the power-on-reset pulse. While the latches requiring initialization by the power-on-reset pulse have been observed to insure that the latches are in an initialized state, that observation has provided no guarantee that the latches are in the initialized state because of a reset pulse. That is, the latches may simply have randomly fallen into an initialized state during the power-up sequence.
The problem is to find an efficient way to determine, without probes or dismantling, whether or not the power-on-reset circuitry of an integrated circuit generates a power-on-reset pulse during the start-up (power-up) sequence of operation.